1. Field of the Invention
The present invention generally relates to integrated circuit test systems, and more particularly to a computer program that analyzes voltage dependency of integrated circuit power supply pin quiescent current measurements.
2. Description of Related Art
Manufacturing tests and design verification tests are necessary for ensuring functionality and reliability of large-scale digital integrated circuits such as Very Large Scale Integration (VLSI) circuits. Millions of transistors and logic gates are often combined on a single die and the performance of the die is verified both in the design phase and the manufacturing phase of a VLSI product cycle.
Power supply current for individual gates or blocks within such a VLSI circuit combines to generate the power requirements for the overall die, and will typically combine in sub-groups to several power and ground pins that are typically also connected within the integrated circuit package. Faults within a VLSI circuit are generally caused by short circuit paths or open circuit paths in conductor or semiconductor segments and as device and line size is decreased in order to increase transistor count, a tolerable defect level is established by a manufacturer. Post-manufacture testing is performed, generally at the wafer level, in order to avoid packaging defective devices.
One test that has proven very efficient for determining whether short circuit faults exists in semiconductor dies is a quiescent supply current test (or IDDQ test). IDDQ testing is typically performed by measuring the leakage current through the power supply plane (sum of the power pin or return pin currents, i.e., IDDQ) using a manufacturing tester parametric (analog) measurement capability. A series of test vectors are used to exercise internal states of the integrated circuit and the IDDQ measurements are used to discover states in which an internal short is activated (for example, a short to ground on the output of an inverter raises IDDQ when the input of the inverter is set to a known low state by the test vector pattern).
However, the shorting resistance in short-circuit failures may be relatively high compared to the output circuit resistance and thus a particular short may not be a significant defect requiring rejection of a die. Additionally, a particular test acceptance current level (even on a per-vector basis) may cause rejection of dies that will not exhibit faults because the particular output circuit resistance is low with respect to the shorting resistance. Such a test may also pass dies that will exhibit faults, which may be logic value failures or unacceptable signal delays. Faults may be missed as the output circuit resistance may be so high that even a high shorting resistance that does not appear to significantly affect IDDQ may cause operational failures. Such fault missing may cause parts to be shipped that may exhibit failures in end-user installations, or at least will cost further test time and/or further packaging process cost that could be avoided if the defect could be detected prior to functional testing.
As the output resistance of various gates within a typical VLSI circuit may vary by as much as 100:1, variations in shorting resistance and short location cause some significant defects to be easily masked, while other defects that will not affect the functionality of the die may cause waste due to unnecessarily rejected dies.
Therefore, it is be desirable to implement an improved IDDQ testing methodology that can distinguish between shorts that are likely to cause functional failures and those that will not. It would further be desirable to provide an IDDQ testing methodology that can detect high-resistance shorts that will cause functional failures and detect relatively low-resistance shorts that will not cause functional failures.